1. Field of the Invention
The present invention is related to an integrated packaging structure, and more particularly is related to an integrated packaging structure with two dies integrated into one packaging structure.
2. Description of the Prior Art
Attending with technology development, widely use of electronic devices makes our daily lives more convenient. The power transistors, such as metal-oxide-semiconductor field-effect transistor (MOSFET), are commonly used in the electronic devices. With the advantages of high cell density and low static leakage current, the power transistors are widely used in the circuit design of electronic devices.
It has become a topic for the manufacturers to modify the design of semiconductor packaging structure for the power transistor to meet the trend of a smaller/slimmer semiconductor package. In the conventional packaging structure, if a circuit design with two or more MOSFET integrated circuits (ICs) connected with each other is needed, the two MOSFET ICs would be separately packaged and further connected with each other by using the conductive wires. The long conductive path would result in greater conductive loss, and such design would occupy a significant footprint which restricts the usage of a smaller packaging substrate.